From: https://www.servethehome.com/unbuffered-registered-ecc-memory-difference-ecc-udimms-rdimms/

Error Checking and Correction (ECC) memory is mostly considered essential in enterprise environments 
these days. Single bit error checking and correction within an 8-bit byte allows for single bit errors
 to be both detected and corrected when they occur. Interestingly enough, the way this single bit ECC 
works is not all that unlike RAID 4 and RAID 5 where an XOR algorithm is used to generate parity bits. 
Instead of losing usable memory capacity, memory makers tend to add an additional chip to ECC memory 
for every eight storage chips. When a single bit error is detected, the parity information is used to 
reconstruct the data with an error. Again, this is conceptually similar to how RAID 4 and RAID 5 can 
scrub and fix data errors in storage arrays. Larger errors than multi-bit can be detected but not 
corrected by the single bit ECC type of parity scheme.